The invention relates to a semiconductor memory device, and in particular to a semiconductor memory device which can perform refresh operation independently of any signal received from the external.
An asynchronous static random access memory (hereinafter referred to as SRAM) which does not need external clocks is used widely for a portable terminal such as a mobile phone. Because a SRAM does not need refresh operation, a complex control for the refresh control is not necessary. Thus a system structure of a portable terminal can be simplified by using SRAMs. Therefore, a SRAM is suitable for a portable terminal.
Recently, a portable terminal is equipped with functions improved to a large degree, so that it is required to have a memory device of larger capacity. The memory cell size of SRAM is about ten times that of a dynamic random access memory (hereinafter referred to as DRAM). Therefore, when a SRAM of large capacity is used for a portable terminal, the cost of the chip is high largely, and this increases the price of the portable terminal. Because a DRAM has a lower cost per bit, it is suggested to use a DRAM, instead of a SRAM, for a portable terminal.
A DRAM has an active state wherein data can be read and written and a standby state wherein the data are retained, and it needs to maintain the stored state by refresh operation. Therefore, it needs a complicated memory control for refresh operation. Thus, it is not easy to adopt DRAMs instead of SRAMs for engineers in portable terminal manufacturers who have designed systems by using SRAMs as memory devices.
Then, a new semiconductor memory device has been developed actively that operates as a DRAM as a memory device, but as a SRAM as to the interaction with the external. Such a new semiconductor memory device is reported in KAZUHIRO SAWADA et al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 23, No. 1, FEBRUARY 1998, p12-19.
Memory cells in the new semiconductor memory device are the same as in a DRAM. On the other hand, the external interface thereof including control signals and address signals is about the same as that of a SRAM. Further, the refresh operation in the new semiconductor memory device is not controlled by an external signal, in contrast to the refresh operation or the self refresh operation in a prior art DRAM, and it is controlled by a refresh enable signal generated periodically by a refresh circuit inside the semiconductor memory device. The above-mentioned new semiconductor memory device can perform refresh operation independently of an external input signal. Therefore, it is called as DRAM having completely hidden refresh function. A refresh circuit includes a timer circuit as a ring oscillator, and it generates a refresh enable signal in correspondence to a cycle signal outputted periodically by the timer circuit. Because the timer circuit generates the cycle signal constantly, the new DRAM performs refresh operation periodically both in the active state and in the standby state. By developing the DRAM having completely hidden refresh function, new high functions can be added to a portable terminal.
However, because the new DRAM performs refresh operation both in the active state and in the standby state, a malfunction may happen when a refresh enable signal is activated at the same timing as a write or output enable signal. This is explained below.
FIG. 1 is a timing chart when a malfunction may happen in a DRAM having completely hidden refresh function. Chip enable signal /CE is a control signal received from the external. (Hereinafter, a signal having xe2x80x9c/xe2x80x9d appended at the top thereof denotes a negative logic signal.) When chip enable signal /CE is active, the DRAM is in the active state, while when inactive, it is in the standby state. In the timing chart shown in FIG. 1, in the standby state until time t4, chip enable signal /CE is inactive (xe2x80x9cHxe2x80x9d level). Thus, the DRAM is in the standby state, and at times t1 and t3, refresh enable signal /REFE is activated in correspondence to the activation of refresh cycle signal /Refcyc so that refresh operation is performed. On the other hand, at time t2 when refresh cycle signal /Refcyc is inactive so that refresh operation is performed. Next, at time t4, chip enable signal /CE becomes the active state (xe2x80x9cLxe2x80x9d level), the DRAM becomes the active state. Therefore, for example at time t5 when refresh enable signal /REFE is activated, a signal for requesting write or read may be received from the external. In such a case, the DRAM is liable to function erroneously.
In order to prevent such a malfunction, a prior art DRAM having completely hidden refresh function has an arbitration circuit. The arbitration circuit compares refresh enable signal /REFE as a synchronization signal with a request signal for write or read to control the order of the operation. In the concrete, when refresh enable signal /REFE and a request signal for write or read are activated at the same timing, the arbitration circuit makes the operation for the signal activated earlier start first and the operation of the other signal start next. Thus, when the two signals are activated at the same time, the malfunction of the DRAM can be prevented to some degree.
However, when the arbitration circuit controls to perform write or read after refresh operation, the access rate is liable to be decreased to a large extent. Further, when refresh enable signal /REFE and a request signal for write or read are activated at absolutely the same timing, the arbitration circuit cannot perform arbitration.
Therefore, it is difficult that the prior art DRAM having completely hidden refresh function secures the stability of refresh operation.
An object of the present invention is to secure the stability of refresh operation in a semiconductor memory device having an active state where data can be read and written and a standby state where the data are retained.
A semiconductor memory device according to the invention has an active state wherein data can be read and written and a standby state wherein the data are retained. The semiconductor memory device has a memory cell array including a plurality of memory cells arranged in a matrix, and a refresh controller which refreshes data stored in the plurality of memory cells. In the refresh controller, a first refresh cycle generator generates a first refresh cycle, while a second refresh cycle generator generates a second refresh cycle having a period shorter than the first refresh cycle. A refresh processor performs refresh operation when the refresh operation becomes possible after the first refresh cycle and, when refresh operation is not performed for a period longer than the first refresh cycle (long period), it performs refresh operations successively based on the second refresh cycle in the long period or after the long period. Thus, when it is not a long cycle or when high speed refresh operation is necessary, refresh operation can be performed at high speed cycle, while when it is a long cycle, refresh operation can be performed automatically in a necessary time. In a long cycle, the device can be operated stably without destroying data. Preferably, a detector in the refresh processor detects that refresh operation is not performed for the long period. Preferably, the detector comprises a counter which counts the first refresh cycle when refresh operation is requested. The long period is detected when the counter counts the first refresh cycle more than a predetermined times. Thus, the long period can be recognized automatically in a simple structure.
An advantage of the present invention is that when refresh operation is not performed for a long period, refresh operation can be performed automatically in a necessary time stably without destroying data.